Recently, three-dimensional NAND flash memory devices are in continuous development. For example, three-dimensional NAND flash memory devices have been fabricated based on terabit cell array transistor (TCAT) technology. These three-dimensional NAND flash memory devices include a plurality of nonvolatile transistors connected in series. Among these transistors, the transistor at the top (referred to as the top transistor) is used as a string select (“SSL”) transistor, and the transistor at the bottom (referred to as the bottom transistor) is used as a common source select (“CSS”) transistor. Further, a gate select line (“GSL”) may turn on the bottom transistor. The bottom transistor includes a portion of the vertical channel and a portion of a horizontal channel on the substrate. The top and bottom selection transistors are simultaneously formed with the formation of other memory cell transistors.
Conventional three-dimensional NAND flash memory devices (e.g., TCAT structures) are manufactured before the back-end-of-line (BEOL) of logic modules. In the manufacturing process of conventional three-dimensional NAND flash memory devices, it is necessary to dope the silicon substrate to form a source or drain of the bottom transistor. Therefore, conventional three-dimensional NAND flash memory devices are directly formed on the silicon substrate. However, a BEOL generally has no silicon substrate, which is typically a dielectric layer (e.g., a metal interlayer dielectric layer). Therefore, conventional three-dimensional NAND flash memory devices are difficult to be form in BEOL processes, that is, conventional three-dimensional NAND flash memory devices are not compatible with the BEOL processing.